1. Field
Example embodiments are directed to a semiconductor memory device and a test method thereof.
2. Description
Semiconductor memory devices are used in various fields and the most widely used memory device is the Dynamic Random Access Memory (DRAM). Dual Data Rate Synchronous DRAM (DDR SDRAM) may write and read data in response to a rising and falling edges of a clock signal and may therefore operate at a high frequency.
FIG. 1 is a timing diagram illustrating a normal mode of operation of DDR SDRAM in the conventional art. FIG. 1 illustrates a JEDEC compliant normal mode of operation involving a burst length of four data bits D0-D3. FIG. 2 is a timing diagram illustrating a test operation of DDR SDRAM in the conventional art.
Referring to FIG. 1, when a READ is input, each bit D0-D3 of a four bit data may be output from a semiconductor memory device in response to a rising and falling edge of a clock signal CLK.
Generally, increase in the frequency of clock signal CLK may cause decrease in clock signal pulse width and width of data bits D0-D3 may decrease. Therefore, it is difficult to read data during test operation and detect errors. In an attempt to overcome the above problems, a High Speed Data (HSD) test mode has been introduced, in which the width of each bit may be increased to at least twice its width during normal operation.
HSD may be explained with reference to FIG. 2. A Test Mode Register Set (TMRS) may set a first test mode during which, when a READ command is input, a first data group, for example even numbered data bits comprising D0, D2, etc., is output. TMRS may then set a second test mode during which, when a READ command is input a second data group, for example odd numbered data bits comprising D1, D3, etc., is output. Since, the width of each data bit in the High Speed Data (HSD) test mode may be increased to at least twice its width in normal operation, the data rate may be reduced during the test operation.
Thus, the data groups, for example the first and/or second data group may be tested through a test mode setting through TMRS. Although the high speed data test mode may increase reliability in test, it also may require more time and may reduce productivity.